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The European Space Agency is investigating many ways to boost computing capabilities in space, and one of the processors it is backing is close to release. The space agency is part of a group developing an open-source processor called Occamy, which is based on RISC-V. The chip was closer to completion and is now being assembled after being taped out late last year, researchers said during a presentation at last month’s Design, Automation and Test in Europe Conference. The 432-core chip is an interesting combination of old and new tech, and has been designed using the relatively new chiplet approach. The chiplet design allows the mixing and matching of old and new technologies - such as analog or digital processors - inside a chip package. Occamy is a low-power chip for AI and high-performance computing workloads. AI workloads today largely rely on accelerators like GPUs and AI cores for training and inferencing, and the researchers hope the open-source chip could also be used in earth-bound AI workloads. The chip is being developed as part of the EuPilot program, which is developing homegrown processors to reduce reliance on proprietary x86 and ARM chips. The core Occamy chip development is being carried out by researchers at ETH Zürich and University of Bologna. The European Processor Initiative is also developing sovereign chips for supercomputers, AI, IoT, and autonomous cars. ESA is interested in the chips because it will allow equipment in space to perform on-chip data analysis. While there is no guarantee that ESA will put the chip in operation, it is one of many processors being explored for spaceflight computing. NASA has also adopted RISC-V chips from Microchip and SiFive to upgrade its spaceflight computers. The researchers designing the Occamy chip are hoping the chip design will be adopted and reproduced for use in more applications. Occamy is a unique mix of low-overhead CPU cores, AI accelerators, and memory cores. The chiplet includes two computing tiles - each with 216 RISC-V cores - with two 16GB HBM2e memory cores. The design also includes 64-bit floating point units for matrix calculations. The cores are connected through a silicon interposer. The chip has a total of around 1 billion transistors over 72mm^2, which is about the same as a quad-core Sandy Bridge chip made by Intel in 2011 (which was three times larger). The RISC-V chip delivers about 0.75 teraflops of FP64 performance, or 6 teraflops of FP8 performance. The chip does not need cooling fans. The core RISC-V design has a compact instruction set, and acceleration modules can be tacked on top of it. The flexibility allows ESA to design hardened compute modules that do not break and can withstand extreme temperatures in space. Occamy has a lightweight 32-bit CPU core that acts more as a control chip, and it is responsible for rerouting tasks to the AI cores, which are extensions to the instruction set architecture. The HBM2e memory tile was provided by Micron, and the chip is being manufactured by Globalfoundries on the 12-nanometer low-power process. The design intends to support high-performance and AI workloads through a bare-metal runtime, according to the slides presented at the DAC conference. It is not yet clear if the runtime will be at a container level, or at the bare-metal level which requires no intervention from the OS. The intent of the researchers is for the chip to be replicated at a low cost, and the implementation could depend on the software. The Occamy chip design can be mapped to FPGAs. It can be tested on two AMD Xilinx Virtex UltraScale+ HBM FPGAs, which has HBM memory, or on the Virtex UltraScale+ VCU1525 FPGA. Dr.Gonzo Oh sheeeet. @kjepphesten, @reclusivestoner @pusur: I hope you drown in a septic tank full of sheeeeet. You would feel right at home in it i bet!:) May 9, 2023